LOGBOOK

HELP

1 / 81
Other keys: showSpace: good1-4: rate0: skip5: flag

Question

What basic cycle does a processor repeat for every instruction?

Answer

Fetch → decode → execute, repeated endlessly as long as there is power — the processor reads the next instruction, works out what it means, and carries it out.

A three-step loop: fetch the next instruction, decode it, execute it, then repeat.

* A processor endlessly repeats fetch, decode and execute for each instruction, as long as it has power. *

At its heart a CPU is a simple loop. It maintains a program counter (the address of the next instruction), and on each turn it:

  1. Fetches the next instruction — which raises the questions "what is the next instruction?" and "fetch it from where?"
  2. Decodes it — works out the instruction format, which operation it is, what operands it takes, and where those operands come from and go to.
  3. Executes it — actually performs the operation, then advances the program counter and loops.

Everything else in this topic hangs off this cycle. The ISA is the agreement that answers the decode questions (what instructions exist, what operands mean); the registers and memory are where operands live; the condition codes record results of execution; and control instructions (jumps, calls) change which instruction gets fetched next. Keeping this fetch-decode-execute loop in mind turns a pile of assembly facts into one coherent picture.

Go deeper:

This is a simple diagram illustrating the individual stages of the fetch-decode-execute cycle. Legend:
PC – Program counterMAR – Memory address registerMDR – Memory data registerCIR – Current instruction registerCU – Control unitALU – Arithmetic logic unit
This is a simple diagram illustrating the individual stages of the fetch-decode-execute cycle. Legend: PC – Program counterMAR – Memory address registerMDR – Memory data registerCIR – Current instruction registerCU – Control unitALU – Arithmetic logic unit
HydenB · CC BY-SA 4.0 · Wikimedia Commons
or press any other key

Question

What is an Instruction Set Architecture (ISA)?

Answer

The ISA is the visible interface between hardware and software — the "contract" defining everything a programmer needs to know to reason about the machine, while hiding how it is built.

Vertical stack of layers with the ISA as the hardware/software interface in the middle.

* The ISA is the contract that splits the stack: how you program the machine above, what gets built in hardware below. *

A processor is enormously complex inside, but software shouldn't have to care about transistors and pipelines. The ISA draws a clean line: above it, compilers and programmers see a stable set of instructions, registers, and rules; below it, hardware designers are free to implement those however they like. As Amdahl, Blaauw and Brooks put it in 1964, the ISA is "the conceptual structure and functional behavior as seen by the programmer, as distinct from the data flow, logical design, and physical implementation."

What the ISA specifies:

  • The instructions available (what operations exist)
  • Data types and their sizes
  • The registers (how many, how wide, their roles)
  • How memory is addressed (byte ordering, addressing modes)
  • The execution model (interrupts, exceptions, privilege)

Why it matters: because the contract is stable, the same binary runs on a simple in-order chip and a complex out-of-order superscalar one. The ISA "tells us what the processor will do, but not how it does it."

Analogy: an ISA is like a restaurant menu — you order dishes (instructions) without needing to know how the kitchen (the microarchitecture) prepares them.

Go deeper:

One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.
One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.
en:User:Booyabazooka · CC BY-SA 3.0 · Wikimedia Commons
or press any other key